Semiconductor chips have become progressively more complex, driven in large part by the need for increasing processing power in a smaller chip size for compact or portable electronic devices such as cell phones, smart phones, personal media systems, or ultraportable computers.
A redistribution layer (RDL) can allow the use of smaller chip sizes while still having access to all contact points. The RDL can be formed in a “fan-in” or “fan-out” configuration, depending on the application. However, creating the RDL at small scales with the required precision can be a time-consuming and expensive process.
The RDL having non-insulated traces, or “fan-in” “fan-out” traces, brings up a risk of bump bridges in fine bump pitch flip chip applications. The fine bump pitch flip chip applications have smaller spacing between the non-insulated traces, resulting in the risk of the bump bridges. The bump bridges can create unwanted electrical connection shorting the bumps and the adjacent traces, causing circuit failures or malfunctions.
Thus, a need still remains for a precise and cost-effective way of creating an RDL. In view of the shrinking sizes of electronic components, it is increasingly critical that answers be found to these problems. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.